Lead Digital ASIC Circuit Design Engineer

RELOCATION ASSISTANCE: Relocation assistance may be available

CLEARANCE TYPE: SCI

TRAVEL: Yes, 10% of the Time

At Northrop Grumman, we offer extraordinary opportunities for individuals eager to work on groundbreaking systems that will influence lives globally today and into the future. With a legacy of innovation that includes milestones such as the first transatlantic flight, stealth technology, and lunar exploration, we seek individuals with bold ideas, courage, and a pioneering spirit to help shape the future while enjoying the journey. Our culture is built on intellectual curiosity and diversity, valuing each employee's unique contributions as we strive to accomplish what others deem impossible. Join us in making history.

The Northrop Grumman Mission Systems (NGMS) Advanced Processing Solutions Business is at the forefront of innovation, redefining extreme technologies and advancing scientific exploration. We are delving into the realm of Transformational Computing, leveraging the unique properties of superconductivity and quantum mechanics to create revolutionary, energy-efficient computing systems.

As a member of our team, you’ll contribute to extending the bounds of computing beyond Moore's Law through innovative computer architectures, processing and memory subsystems, and large-scale high-performance systems. Collaborate with a diverse team of scientists and engineers in a dynamic environment to bring these processing solutions to fruition, offering remarkable advantages to the warfighter.

We are currently looking for an innovative front-end ASIC design engineer specializing in the design and verification of full-custom digital circuits. The ideal candidate will have expertise in Verilog, System Verilog, or VHDL RTL coding, the ability to write complex functional test benches, and a solid understanding of synchronous digital design concepts. You will be skilled in developing functional verification plans based on circuit requirements and generating manufacturing test plans. Familiarity with synthesis, SDC constraints, formal verification, and static timing is essential. Knowledge of scan insertion and ATPG is a bonus and experience working with place and route engineers to optimize floor planning and clock tree constraints for timing closure is a must. Strong communication skills, both written and oral, are crucial.

Key Responsibilities

• Behavioral coding of circuits using Verilog, System Verilog, or VHDL RTL
• Conduct circuit synthesis, formal verification, and static timing analysis utilizing state-of-the-art digital ASIC design tools
• Create verification plans based on circuit requirements and develop circuit functional test benches in RTL
• Generate manufacturing test vectors and establish manufacturing circuit test plans
• Assist in developing automated procedures to enhance digital design processes

This position requires 100% onsite work at our Advanced Technology Lab in Linthicum, MD.

Candidate must be a US Citizen and have the ability to obtain and maintain a security clearance once onboard.

This position can be filled at either the Principal level or the Senior Principal level. Qualifications for both roles are detailed below:

Basic Qualifications for Principal Digital ASIC Circuit Design Engineer Level:

• Bachelor’s degree in a technical area (BSEE or related Engineering discipline preferred) with 5 years of relevant experience (3 years with a STEM MS or 1 year with a STEM PhD)
• Experience through the full product life cycle (requirements, design, implementation, test) of ASIC design
• Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion)
• Proficiency with current ASIC design tools for all phases described, including: Simulation - Mentor ModelSim, Cadence Excelium, Incisive, or Synopsys VCS; Synthesis - Synopsys Design Compiler, Cadence Genus, or Cadence RTL Compiler; Static Timing - Synopsys Primetime or Cadence Tempus
• Candidate must be a US Citizen and have the ability to obtain/maintain a security clearance once onboard.

Preferred Qualifications

• Advanced degree - MS or PhD
• Current security clearance or eligibility
• Experience with chip level integration and acting as an ASIC chip lead; strong design automation skills
• Background in CAD design network, tool configuration, and data management
• Familiarity with custom layout in Virtuoso and physical verification (LVS/DRC) in Assura or Calibre; knowledge of EDA standards used in cell/library development and modeling (Liberty timing model, SDC)

Basic Qualifications for Sr. Principal Digital ASIC Circuit Design Engineer Level:

• Bachelor's degree in a technical area (BSEE or related Engineering discipline preferred) with 8 years of relevant experience (6 years with a STEM related MS or 4 years with a STEM related PhD)
• Experience through the full product life cycle (requirements, design, implementation, test) of ASIC design
• Working knowledge of the front-end ASIC design flow from RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion)
• Proficiency with current ASIC design tools for all phases described, including: Simulation - Mentor ModelSim, Cadence Excelium, Incisive, or Synopsys VCS; Synthesis - Synopsys Design Compiler, Cadence Genus, or Cadence RTL Compiler; Static Timing - Synopsys Primetime or Cadence Tempus

Preferred Qualifications

• Advanced degree - MS or PhD
• Current security clearance
• Experience with chip level integration and as an ASIC chip lead; strong design automation skills
• Experience in CAD design network, tool configuration, and data management

Salary Range for Principal Level: $119,600.00 - $179,500.00

Salary Range for Senior Principal Level: $149,300.00 - $186,600.00

The above salary ranges are guidelines; the final salary is determined based on the role's scope and responsibilities, as well as the candidate's experience, education, skills, and current market conditions. Depending on the position, employees may be eligible for overtime, shift differentials, and discretionary bonuses in addition to base pay. Annual bonuses reward individual contributions and enable employees to share in company successes. Employees in Vice President or Director roles may qualify for Long Term Incentives. Northrop Grumman also offers a wide range of benefits, including health insurance, life and disability coverage, a savings plan, and paid time off for vacations and personal matters.

The application period for this position is approximately 20 days from the posting date, subject to adjustment based on business needs and candidate availability.

Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or other protected classes. For more information on our commitment to equal opportunity, please consult our EEO and pay transparency statement. Note: U.S. Citizenship is required for all positions requiring government clearance and certain other restricted roles.